Important

SymbiFlow is now F4PGA. See f4pga.org and f4pga.readthedocs.io.

References

R1

Vikram Adve, Chris Lattner, and LLVM Developer Group. LLVM Project, a collection of modular and reusable compiler and toolchain technologies. 2003. URL: https://www.llvm.org/.

R2

Tim Ansell and Mehdi Saligane. The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : Invited Paper. In 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1–8. 2020. URL: https://dl.acm.org/doi/abs/10.1145/3400302.3415736.

R3

Georg Brandl, Takeshi KOMIYA, and contributors. Sphinx, Python Documentation Generator. 2007. URL: https://www.sphinx-doc.org.

R4

Tony Bybell and contributors. GTKWave: a is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX. 1998. URL: https://github.com/gtkwave/gtkwave.

R5

Aliaksei Chapyzhenka and contributors. Wavedrom, digital timing diagram rendering engine. 2014. URL: https://github.com/wavedrom/wavedrom.

R6

Alain Dargelas and Henner Zeller. Universal Hardware Data Model. In Workshop on Open-Source EDA Technology 2020 (WOSET). 10 2020. URL: https://woset-workshop.github.io/PDFs/2020/a10.pdf.

R7

Alain Dargelas, Henner Zeller, and contributors. Surelog, SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. 2019. URL: https://github.com/alainmarcel/Surelog/.

R8

David Fang, Henner Zeller, and contributors. Verible, a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter. 2019. URL: https://chipsalliance.github.io/verible/.

R9

gatecat and contributors. nextpnr: portable FPGA place and route tool. URL: https://github.com/YosysHQ/nextpnr.

R10

Tristan Gingold and contributors. GHDL: open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. Sep 2003. URL: https://github.com/ghdl/ghdl.

R11

Tristan Gingold and contributors. ghdl-yosys-plugin: VHDL synthesis (based on ghdl and yosys). 2017. URL: https://github.com/ghdl/ghdl-yosys-plugin.

R12

Andrew B. Kahng. Open-Source EDA: If We Build It, Who Will Come? In 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 1–6. 2020. doi:10.1109/VLSI-SOC46417.2020.9344073.

R13

Kevin E. Murray, Mohamed A. Elgammal, Vaughn Betz, Tim Ansell, Keith Rothman, and Alessandro Comodi. SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs. IEEE Micro, 40(4):49–57, 2020. doi:10.1109/MM.2020.2998435.

R14

Kevin E. Murray, Oleg Petelin, Sheng Zhong, Jia Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron G. Graham, Jean Wu, Matthew J. P. Walker, Hanqing Zeng, Panagiotis Patros, Jason Luu, Kenneth B. Kent, and Vaughn Betz. VTR 8: High-Performance CAD and Customizable FPGA Architecture Modelling. ACM Trans. Reconfigurable Technol. Syst., May 2020. URL: https://doi.org/10.1145/3388617, doi:10.1145/3388617.

R15

Austin Rovinski, Tutu Ajayi, Minsoo Kim, Guanru Wang, and Mehdi Saligane. Bridging Academic Open-Source EDA to Real-World Usability. In 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1–7. 2020. URL: https://dl.acm.org/doi/10.1145/3400302.3415734.

R16

Wilson Snyder and contributors. Verilator, FOSS tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. 2003. URL: https://www.veripool.org/verilator/.

R17

Richard Stallman and contributors. GCC, the GNU Compiler Collection. May 1987. URL: https://gcc.gnu.org/.

R18

Richard Stallman and GNU Project. GDB: The GNU Project Debugger. 1986. URL: https://www.gnu.org/software/gdb/.

R19

Kevin Thibedeau. Symbolator, a component diagramming tool for VHDL and Verilog. URL: https://kevinpt.github.io/symbolator.

R20

Stephen Williams and contributors. Icarus Verilog, a Verilog simulation and synthesis tool. URL: http://iverilog.icarus.com/.

R21

Claire Wolf and contributors. SymbiYosys: front-end for Yosys-based formal verification flows. URL: https://github.com/YosysHQ/SymbiYosys.

R22

Claire Wolf and contributors. Yosys Open SYnthesis Suite. URL: https://github.com/YosysHQ/yosys.

R23

Clifford Wolf and Johann Glaser. A Free Verilog Synthesis Suite. In Proceedings of Austrochip 2013. 2013. URL: https://yosyshq.net/yosys/.