SymbiFlow

Table Of Contents

SymbiFlow documentation

• Introduction
  • EDA Tooling Ecosystem
  • Project structure
  • Current status of bitstream documentation
• Toolchain description
  • Getting Started with SymbiFlow Toolchain development
    • Clone repository
    • Prepare environment
    • Build example
    • Load bitstream
  • FPGA Design Flow
    • Synthesis
    • Place & Route
    • Bitstream translation
  • Yosys
    • Short description
    • Usage in Toolchain
    • Output analysis
    • Technology mapping in SymbiFlow toolchain
    • Technology mapping for VPR
    • More information
  • VPR
    • Basic flow
    • Command-line Options
    • Graphics
    • Timing Constraints
    • SDC Commands
    • File Formats
    • Debugging Aids
    • Placer and Router Debugger
• SymbiFlow Architecture Definitions
  • Contents
    • Getting Started with SymbiFlow Toolchain development
    • Project X-Ray
    • Development Practices
• Project X-Ray
  • Introduction
    • Collected information
    • Methodology
    • Important Parts
  • Getting Started
    • Project X-Ray
    • Quickstart Guide
    • C++ Development
    • Process
    • Database
    • Current Focus
    • Contributing
  • Xilinx 7-series Architecture
    • Overview
    • Configuration
    • Bitstream format
    • Interconnect PIPs
    • Distributed RAMs (DRAM / SLICEM)
    • Glossary
    • References
    • Contributor Covenant Code of Conduct
    • Guide to updating the Project X-Ray docs
  • Database Development Process
    • Project X-Ray
    • Quickstart Guide
    • C++ Development
    • Process
    • Database
    • Current Focus
    • Contributing
    • Contributing to Project X-Ray
    • Adding New Fuzzer
    • Fuzzers
    • Minitests
    • Tools
    • Guide to adding a new device to an existing family
  • Database
    • Description
    • Common database files
    • Part specific database files
• Welcome to Project Trellis
  • Overview
  • Tiles
    • Logic Tiles
    • Common Interconnect Blocks (CIBs)
    • IO Tiles
    • Global Clock Tiles
    • Embedded Block RAM (EBR)
    • DSP Tiles
    • System and Config Tiles
  • General Routing
  • Global Routing
    • Mid Muxes
    • Centre Muxes
    • Spine Tiles
    • TAP_DRIVE Tiles
    • Non-Clock Global Usage
  • Bitstream format
    • Basic Structure
    • Control Commands
    • Configuration Data
    • Compression Algorithm
    • Partial Bitstreams
    • Device-Specific Information
  • Glossary
  • Database Development Overview
    • NCL Files
    • Fuzzers
  • libtrellis Overview
    • Bitstream
    • Chip
    • CRAM
    • Tile
    • TileConfig
    • TileBitDatabase
    • RoutingGraph
    • DedupChipdb
    • ChipConfig
  • Textual Configuration Format
    • Overview
    • Non-Tile Configuration
    • Tile Configuration
    • Conversion
  • DSP Support
    • Structure
    • Multiplier
    • Adder
    • Macs
• FPGA Assembly (FASM) Specification
  • Introduction
  • File Syntax description
    • Lines
    • Annotations
    • Formal syntax specification of a line of a FASM file
    • Canonicalization
  • Meaning of a FASM line
    • Feature
    • FeatureAddress and FeatureValue

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Introduction